arena: rename inner-SIMD-align knob and drop default 64 -> 32#552
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…4 -> 32 Rename the in-arena element-storage alignment knob to TA_ARENATENSOR_SIMD_ALIGN (matching the TA_ prefix used by every other TA CMake option/var), and wire it through the same CMake -> config.h.in -> header pipeline as TA_MAX_SOO_RANK_METADATA. The previous TILEDARRAY_INNER_SIMD_ALIGN was a header-only #ifndef/#define knob with no CMake surface; the new form is a proper cache variable, documented in INSTALL.md. Drop the default from 64 B to 32 B: 32 B covers AVX2 YMM loads/stores (the most common x86_64 SIMD target today) and shaves 32 B/cell off the in-arena padding. AVX-512 builds that want a wider floor are one `-DTA_ARENATENSOR_SIMD_ALIGN=64` away. The doc comment and INSTALL.md entry also call out the NEON / Apple-Silicon options (16 / 128). No backward-compatible alias for the old macro/constant names -- there are no external users yet.
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Summary
Two related changes to the ArenaTensor in-cell alignment knob in
src/TiledArray/tensor/arena_tensor.h:TILEDARRAY_INNER_SIMD_ALIGN→TILEDARRAY_ARENATENSOR_SIMD_ALIGN(andkInnerSimdAlign→kArenaTensorSimdAlign), so the knob's name reflects the type whose layout it parametrizes. Hard cut — no compat alias, since there are no external users yet.data_offsetper inner cell. AVX-512 builds that want the wider floor stay one-DTILEDARRAY_ARENATENSOR_SIMD_ALIGN=64away.Why this matters: each
ArenaTensorcell pads fromsizeof(Cell)(~14 B forbtas::zb::RangeNd<>) up to this alignment before its element storage, so per-inner-cell bookkeeping isdata_offset + 8 B view ptr. On a ToT tile with millions of inner cells (e.g. PNO-CCSD), the difference between 32 B and 64 B padding is order ~100s of MB of memory.The doc comment now spells out the reasonable overrides:
Test plan
arena_suite,arena_kernels_suite,arena_einsum_unit_suite,arena_tot_trivial_suite,arena_sizeof_invariant_suite,arena_tensor_suite,arena_tensor_kernels_suiteall pass against the new default (np=1, debug build,TA_ASSERT_POLICY=TA_ASSERT_THROW).